1. Field
This disclosure relates generally to semiconductor manufacturing, and more specifically, to the integration of logic transistors and NVM cells.
2. Related Art
Non-volatile memories (NVMs) are often formed on an integrated circuit which also performs other functions. In such cases it is undesirable to sacrifice logic performance in favor of performance of the NVM. Also, it is important to avoid or minimize additional cost in achieving high performance for both the logic and the NVM. Gate last, which is a technique for enhancing performance by using a dummy gate on, typically, thermal oxide for the formation of source/drain regions and then replacing the dummy gate and thermal oxide with a higher performance gate or gate stack and gate dielectric has shown promise or by forming the higher performance gate dielectric relatively early in the process with the high performance gate or gate stack replacing a dummy gate formed over the higher performance gate dielectric. The higher performance gate will typically have higher conductance and an optimized work function. The higher performance gate dielectric will typically have a higher dielectric constant (k) than oxide.
Accordingly there is a need to provide further improvement in achieving high performance while also addressing cost increase issues in integrated circuits that have both NVM and logic, particularly in the context of gate last.